The present disclosure relates to a nonvolatile memory device and a method of fabricating the same, and more particularly, to a nonvolatile memory device including a charge capturing layer and a method of fabricating the nonvolatile memory device.
A memory device is classified into a volatile memory device and a nonvolatile memory device according to whether data is preserved or not when the power is cut off. The volatile memory device is a memory device data of which is lost when the power is cut off, and its examples include a dynamic random access memory (DRAM) device and a static random access memory (SRAM) device. On the other hand, the nonvolatile memory device is a memory device data of which is preserved even when the power is cut off, and a flash memory device is an example of the nonvolatile memory device.
Hereinafter, the nonvolatile memory device will be explained in detail with reference to a figure.
FIG. 1 illustrates a cross-sectional view of a nonvolatile memory device including a conventional gate pattern.
Referring to FIG. 1, a tunnel dielectric layer 11 is formed on a substrate 10. Herein, the tunnel dielectric layer 11 is provided as an energy barrier for the tunneling of charges and may include an oxide layer.
Then, a charge capturing layer 12 is formed on the tunnel dielectric layer 11. The charge capturing layer 12 is provided as a practical data storage and its threshold voltage is changed by supplying or removing charges to or from the charge capturing layer 12. For instance, in a programming operation, charges of a bulk are supplied to the charge capturing layer 12 through the Fouler-Nordheim tunneling (F—N tunneling) and, in an erasing operation, charges captured in the charge capturing layer 12 are discharged into the bulk by the F-N tunneling, so that the threshold voltage is changed.
Subsequently, a charge blocking layer 13 is formed on the charge capturing layer 12. The charge blocking layer 13 plays a role of preventing the charges from passing through the charge capturing layer 12 and moving into a gate electrode 14.
After forming a conducting layer for a gate electrode 14 on the charge blocking layer 13, the conducting layer 14, the charge blocking layer 13 and the charge capturing layer 12 are sequentially etched. As a result, there is formed a gate pattern including the charge capturing layer 12, the charge blocking layer 13 and the conducting layer 14 that are patterned.
Meanwhile, the nonvolatile memory device is classified into a charge storage type nonvolatile memory device and a charge trap type nonvolatile memory device according to a data storage scheme. The charge storage type nonvolatile memory device includes a charge capturing layer formed with a charge storage layer and the charge trap type nonvolatile memory device includes a charge capturing layer formed with a charge trap layer.
Hereinafter, there will be described an energy band diagram in an erasing operation of each of the charge storage type nonvolatile memory device and the charge trap type nonvolatile memory device.
FIG. 2A illustrates an energy band diagram of a conventional charge storage type nonvolatile memory device.
As shown in FIG. 2A, the charge storage type nonvolatile memory device stores data by storing charges in a conduction band of a charge storage layer and erases data by discharging charges stored in the charge storage layer into the bulk through the F-N tunneling by supplying an erasing voltage to the bulk.
Herein, the data erasing operation by the F-N tunneling is influenced by a potential barrier Φ1 of the interface between a charge storage layer 12A and a tunnel dielectric layer 11, a thickness W1 of the potential barrier profile, and a voltage drop −V1 of the tunnel dielectric layer 11 that is generated when the erasing voltage is supplied.
If the erasing voltage is supplied to the bulk, the voltage drop −V1 occurs at an interface between a substrate 10 and the tunnel dielectric layer 11 and thus a triangular potential barrier region A is formed. Since the thickness W1 of the potential barrier is relatively small in the triangular potential barrier region A, the charges stored in the charge storage layer 12A are discharged into the substrate 10 by the F-N tunneling, if the voltage drop −V1 has a greater value than the potential barrier Φ1. Therefore, the charge storage type nonvolatile memory device has a high programming/erasing speed due to the F-N tunneling.
However, because the charge storage type nonvolatile memory device stores the charges in the conduction band, it is prone to interference that is caused by neighboring memory cells. In particular, since the interference effect caused by neighboring memory cells increases as an interval between memory cells is reduced, the conventional charge storage type nonvolatile memory device has a limitation in enhancing the degree of integration of memory devices.
FIG. 2B illustrates an energy band diagram of a conventional charge trap type nonvolatile memory device.
As shown in FIG. 2B, the charge trap type nonvolatile memory device stores data by trapping charges in a deep level trap site in a charge trap layer 12B. Herein, the deep level trap site is generally located in a deeper level than a conduction band (e.g., between the conduction band energy level Ec and the valence band energy level Ev), and the energy level of the trap site can be adjusted by changing the composition of the charge trap layer 12B.
As described above, since the charge trap type nonvolatile memory device traps the charges in the trap site of the charge trap layer 12B, its interference effect caused by neighboring cells becomes less than that of the charge storage type nonvolatile memory device. Therefore, the charge trap type nonvolatile memory device is more appropriate for enhancing the degree of integration of the memory devices than the charge storage type nonvolatile memory device.
However, since the charge trap type nonvolatile memory device performs an erasing operation by de-trapping ({circle around (1)}) the charges trapped in the deep level trap site to the conduction band and then discharging the de-trapped charges to the bulk through the F-N tunneling ({circle around (2)}), it requires a relatively high erasing voltage in the erasing operation. That is, the charge trap type nonvolatile memory device has a lower erasing speed than the charge storage type nonvolatile memory device.
It is certainly possible to consider a scheme of improving the erasing speed by adjusting the composition ratio of the charge trap layer 12B. However, since the data preserving characteristic and the data erasing speed of the charge trap type nonvolatile memory device establish a trade-off relationship, the data preserving characteristic is deteriorated when increasing the data erasing speed. For instance, in the case that the charge trap layer 12B is formed with a silicon nitride layer, if a percentage of silicon is increased, the erasing speed can be increased while the data preserving characteristic is deteriorated.
Thus, in order to overcome the characteristic deterioration of the memory device due to the interference effect and to further improve the degree of integration of the memory device, there is a need for a charge trap type nonvolatile memory device having a high data erasing speed and an excellent data preserving characteristic, and a method of fabricating the same.